The bit transmission layer or physical layer (PHY) is the bottom layer in the O[pen]S[ystems]I[nterconnection] layer model, also called OSI reference model and denotes a layer model of the International Standards Organisation (ISO) which in turn serves as a design basis for communication protocols in computer networks.
The physical layer (PHY) is responsible for Combining, F[orward]E[rror]C[orrection], modulation, power control, spreading (C[ode]D[ivision]M[ultiple]A[ccess]) and the like and knows neither data nor applications, only zeros and ones. PHY makes logical channels (transport channels for U[niversal]M[obile]T[elecommunications]S[ystem]) available to the security layer (D[ata]L[ink]L[ayer]) above it, in particular to a partial layer called M[edia]A[ccess]C[ontrol] Layer.
In principle D-PHY provides a flexible, low-cost and quick serial interface for communication links between components within a mobile device.
As illustrated in FIG. 5A, in modern mobile phones a data source, for example an application processor, provides image data as D-PHY signals to the M[obile]I[ndustry]P[rocessor]I[nterface]-D[isplay]S[erial]I[nterface] for display on a connected data sink, for example on a connected display. Also, a data sink such as an application processor, can receive, via a MIPI-C[amera]S[erial]I[nterface], image data in D-PHY format from a connected data source, such as from a connected camera.
A DSI or DSI-2 or CSI or CSI-2 or CSI-3 based on the D-PHY protocol comprises up to four differential data lines and a differential clock line, which electrically connect the application processor by means of a copper cable with the display and/or with the camera. The data rate per differential data line is up to 1.5 Gbps (Gigabit per second).
This conventional sending and receiving of the D-PHY-DSI signals or the D-PHY-CSI signals via one to four differential data signals and a differential clock line is illustrated by way of example in the D-PHY interface configuration of FIG. 5B by way of two bidirectional data channels (=so called data lanes CH0+, CH0− and CH1+, CH1−) and a clock line (=so called clock lane CLK+, CLK−) between the modules of the master side (=data source, for example camera and/or application processor) and the modules of the slave side (=data sink, for example application processor and/or display unit). In the bidirectional multiple data lane configuration the abbreviation PPI in FIG. 5B stands for PHY Protocol Interface.
In this context, as can be seen in FIG. 5A, up to ten copper lines are required for data transmission for each connected display or for each connected camera (for example four times two data lines and one time two clock lines). Correspondingly high-resolution screens, television sets or cameras for example comprise an electrical M[obile]I[ndustry]P[rocessor]I[nterface]-D-PHY-data transmission interface.
Via this interface both H[igh]S[peed] data and L[ow]P[ower] data is transmitted, wherein the data rate of the LP data is typically much less than the data rate of the HS data. This is illustrated in FIG. 4, in which the respective voltage levels are shown for HS data transmission and for LP data transmission.
The electrical link between the D-PHY data transmission interface of the data source and the D-PHY data transmission interface of the data sink can be established galvanically by means of copper cables/electric lines on printed circuit boards, wherein the D-PHY HS signals of a D-PHY data link per differential twisted pair of a copper cable shall be able to support, as already mentioned above, data transmission rates of several gigabit per second.
This implies that very high-quality and therefore expensive copper cables have to be used, if larger distances are to be covered between the data source and the data sink. An alternative to such high-quality and costly copper cables is the serialised optical signal transmission via an optical waveguide, in particular via glass fibre or via plastic fibre.
This serial interface can also be used for transmitting LP data, for example by adding the LP data to the input of a multiplexer which also bundles the HS data for serial transmission.
However, if then only serial transmission is available for the transmission of the LP data, it is no longer possible to transmit in particular static LP data without consuming power. Power consumption is governed by the activity of the multiplexer/the demultiplexer for realising serial data transmission.